Buffer/driver for low dropout regulators

ABSTRACT

The buffer/driver for low dropout regulators (LDO) uses a feedback amplifier with low output impedance to drive the gate of the pass device MP 6  of the regulator. This effectively pushes the gate pole out to a higher frequency. The feedback amplifier is designed for very high slew rate and high bandwidth while running at very low quiescent current. The circuit enhances the LDO performance, stability, and slew rate.

FIELD OF THE INVENTION

[0001] This invention generally relates to electronics and moreparticularly to buffer circuits for low dropout regulators.

BACKGROUND OF THE INVENTION

[0002] In low voltage, low dropout linear voltage regulators (LDO), alarge pass device (typically a FET) must be used to deliver highcurrents to a load. The size of this pass device results in a largeparasitic capacitance seen from the gate of the device to AC ground.This capacitance must be charged and discharged as the load changes inorder to keep the output voltage of the LDO constant. The performance ofthe LDO is therefore limited by how fast this capacitance can be chargedand discharged (slew rate).

[0003] Additionally, the presence of the large parasitic capacitanceresults in a significant pole in the frequency response of theamplifier, which can make the amplifier more difficult to stabilize.

[0004] In most LDO amplifiers a source follower (or, emitter follower)is used to drive the gate of the pass FET. Typical class A followers areslew rate limited in one direction by the biasing current source.

[0005] Prior art solutions to this problem typically involve using largeamounts of quiescent current to decrease the output impedance of thedriver (follower) and to push the gate pole to a higher frequency. Also,many other prior art designs achieve improved slew rate performance byincreasing the bias current through the driver.

SUMMARY OF THE INVENTION

[0006] A buffer/driver for low dropout regulators (LDO) uses a feedbackamplifier with low output impedance to drive the gate of the pass deviceof the regulator. This effectively pushes the gate pole out to a higherfrequency. The feedback amplifier is designed for very high slew rateand high bandwidth while running at very low quiescent current. Thecircuit enhances the LDO performance, stability, and slew rate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings:

[0008]FIG. 1 is a schematic circuit diagram of a preferred embodimentdriver circuit;

[0009]FIG. 2 is a graph of the open loop AC gain and phase response ofthe circuit of FIG. 1;

[0010]FIG. 3 is a graph of the transient response of the preferredembodiment driver of FIG. 1 under the same bias and loading conditionsof FIG. 2;

[0011]FIG. 4 is a graph of the DC transfer characteristics of the drivercircuit of FIG. 1;

[0012]FIG. 5 is a block diagram showing the circuit of FIG. 1implemented in a low dropout regulator;

[0013]FIG. 6 is a schematic circuit diagram of an implementation of alow dropout regulator that uses the drive circuit of FIG. 1;

[0014]FIG. 7 is a graph of the open loop AC gain and phase response ofthe circuit of FIG. 6 with a 200 mA load;

[0015]FIG. 8 is a graph of the transient response of the circuit of FIG.6.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0016] The preferred embodiment described below uses a feedbackamplifier with low output impedance to drive the gate. This effectivelypushes the gate pole out to a higher frequency (1 decade per 20 dB ofloop gain of the feedback amplifier). The feedback amplifier is designedfor very high slew rate while running at very low quiescent current. Thecircuit enhances the LDO performance, stability, and slew rate.

[0017]FIG. 1 is a diagram of the preferred embodiment driver circuit.Bias current Ibias flows through resistor R1 and is mirrored from MP0 toMP1 and MP2. The current sourced by MP2 flows into MN4, and is mirroredby MN5. The current sunk by MN5 must flow through MP3, and must comefrom MP1. Care is taken to insure that the current sunk by MN5 is lessthan the current that is supplied by MP1, and the residual current fromMP1 must flow through MN1 into MN2. MN0 mirrors MN1, so the currentthrough MN0 and MN1 are identical. Care is taken that the voltage dropacross resistor R1 is large enough to keep MP1 in the saturation region.The feedback control loop can be traced from MN1 to MP3 to MN2, thenback to MN1. The input is provided at node Vin and the output at nodeVout. The source voltage is provided at node Vcc and ground is at nodegnd. The backgate node PBKG is coupled to the back gates of transistorsMN2, MN4, and MN5.

[0018]FIG. 2 shows the open loop AC gain and phase response of thefeedback loop. The total bias current is 8 μA, and the load capacitanceis 100 pF. The phase margin is approximately 25 degrees.

[0019]FIG. 3 shows the transient response of the preferred embodimentdriver under the same bias and loading conditions of FIG. 2. The risingslew rate is approximately 1 V/μs, and the falling slew rate isapproximately 6 V/μs. A standard source (emitter) follower would require100 uA of quiescent current to achieve 1 V/μs slew rate under thisloading condition.

[0020]FIG. 4 describes the DC transfer characteristics of the buffer.The output common mode range is limited only by the threshold voltage ofMN0.

[0021]FIG. 5 is a block diagram describing how the buffer circuit ofFIG. 1 may be implemented in an LDO. A transconductance amplifier gmdrives the input of the buffer, and the buffer drives the PMOS passtransistor MP6. RC compensation from resistor R2 and capacitor C isincluded for completeness. Resistors R3 and R4 provide the voltagedivider feedback for the LDO. The regulated output voltage is providedat node Vo.

[0022]FIG. 6 is a circuit diagram of one possible implementation of anLDO that uses the drive circuit of FIG. 1. Circuit 20 is the amplifiergm of FIG. 5. Drive circuit 22 is the buffer circuit of FIG. 5 which isthe circuit of FIG. 1. Transistor MP6 and resistors R3 and R4 of FIG. 5are not shown in FIG. 6. Fast transient circuitry 24 is included in thisexample.

[0023]FIG. 7 shows the open loop AC gain and phase response of the LDOof FIG. 6 with a 200 mA load. The slight peaking in the response in theproximity of 5 MHz is due to, the closed loop response of the buffer (25degrees of phase margin).

[0024]FIG. 8 shows the transient response of the LDO of FIG. 6, as loadcurrent is changed from 0 mA to 0.2 A, and back to 0 mA again. Theovershoot seen on the high load to low load transition is due to thechosen compensation method.

[0025] An advantage of the preferred embodiment is that it pushes thegate pole out to a sufficiently high frequency so as to have negligibleadverse effects on the in-band frequency response of the circuit withoutusing a large quiescent current and without compromising slew-rateperformance while maintaining a relatively simple topology. This isaccomplished by using a relatively simple feedback circuit that achievesvery high slew rate without increasing bias currents.

[0026] While this invention has been described with reference to anillustrative embodiment, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiment, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. For example, the use of the preferred embodimentbuffer/driver circuit is not limited to low dropout regulators. It canbe used in any amplifier that has an internal node that has a largecapacitance, or is slew rate limited. It is therefore intended that theappended claims encompass any such modifications or embodiments.

What is claimed is:
 1. A circuit comprising: an amplifier; an outputtransistor; a buffer circuit coupled between an output of the amplifierand a gate of the output transistor, the buffer circuit is operable topush a gate pole of the output transistor to a higher frequency whileusing a low quiescent current and providing a high slew rate.
 2. Thecircuit of claim 1 wherein the buffer circuit comprises: a firsttransistor coupled to the gate of the output transistor and having acontrol node coupled to the output of the amplifier; a second transistorcoupled to the gate of the output transistor and having a control nodecoupled to the output of the amplifier; a third transistor coupled tothe gate of the output transistor; and a fourth transistor having oneend coupled to a control node of the third transistor and a second endcoupled to the second transistor.
 3. The circuit of claim 2 furthercomprising a fifth transistor coupled to the second and the fourthtransistor.
 4. The circuit of claim 3 further comprising a sixthtransistor coupled to a control node of the fifth transistor such that acurrent in the sixth transistor is mirrored in the fifth transistor. 5.The circuit of claim 4 further comprising a bias current node coupled tothe sixth transistor.
 6. The circuit of claim 5 further comprising aseventh transistor coupled to the fourth transistor.
 7. The circuit ofclaim 6 further comprising an eighth transistor coupled to a controlnode of the seventh transistor such that a current in the eighthtransistor is mirrored in the seventh transistor.
 8. The circuit ofclaim 7 further comprising a ninth transistor coupled to the eighthtransistor and having a control node coupled to the sixth transistorsuch that the current in the sixth transistor is mirrored in the ninthtransistor.
 9. The circuit of claim 1 further comprising a resistorfeedback circuit coupled between the output transistor and an input ofthe amplifier.
 10. The circuit of claim 9 wherein the resistor feedbackcircuit comprises a first resistor coupled in series with a secondresistor and the input of the amplifier coupled to a node between thefirst and second resistors.
 11. The circuit of claim 1 furthercomprising an RC circuit coupled between the output transistor and theoutput of the amplifier.
 12. A driver circuit comprising: a firsttransistor coupled to an output node and having a control node coupledto an input node; a second transistor coupled to the output node andhaving a control node coupled to the input node; a third transistorcoupled to the output node; and a fourth transistor having one endcoupled to a control node of the third transistor and a second endcoupled to the second transistor.
 13. The circuit of claim 12 furthercomprising a fifth transistor coupled to the second and the fourthtransistor.
 14. The circuit of claim 13 further comprising a sixthtransistor coupled to a control node of the fifth transistor such that acurrent in the sixth transistor is mirrored in the fifth transistor. 15.The circuit of claim 14 further comprising a bias current node coupledto the sixth transistor.
 16. The circuit of claim 15 further comprisinga seventh transistor coupled to the fourth transistor.
 17. The circuitof claim 16 further comprising an eighth transistor coupled to a controlnode of the seventh transistor such that a current in the eighthtransistor is mirrored in the seventh transistor.
 18. The circuit ofclaim 17 further comprising a ninth transistor coupled to the eighthtransistor and having a control node coupled to the sixth transistorsuch that the current in the sixth transistor is mirrored in the ninthtransistor.